In currently used transistor-transistor logic (TTL) devices and circuits, logical values corresponding to binary "1" and "0" are ordinarily represented at the output by a high level voltage for example in the range of 2.5 to 5 volts and a low level voltage for example in the range of 0 to 0.8 volts. Such TTL output devices and circuits are described for example in U.S. Pat. No. 4,255,670 for "Transistor Logic Tristate Output With Feedback": U.S. Pat. No. 4,287,433 for "Transistor Logic Tristate Output With Reduced Power Dissipation"; U.S. Pat. No. 4,311,927 for "Transistor Logic Tristate Device With Reduced Output Capacitance"; U.S. Pat. No. 4,321,490 for "Transistor Logic Output For Reduced Power Consumption and Increased Speed During Low to High Transition"; and U.S. Pat. No. 4,330,723 for "Transistor Logic Output Device For Diversion of Miller Current". Overall the TTL family of logic circuits including the low power Schottky TTL circuits and the Fairchild Advanced Schottky TTL circuits provide a combination of relatively short propagation delays with relatively low power dissipation.
On the other hand, emitter coupled logic (ECL) circuits and devices which provide higher speed switches, generally operate at negative voltage with the high and low level voltage signals established on either side of a negative reference voltage typically in the range of -1.2 to -2.0 volts. For example with a reference voltage of -1.2 volts, the high level voltage signal is in the range of for example -0.8 volts while the low level voltage signal is in the range of -1.6 volts. For a reference voltage of -2.0 volts, the high level voltage signals may be in the order for example of -1.6 volts with the low level voltage signals in the order of for example -2.4 volts.
The typical TTL output device or TTL internal buffer circuit includes a pull-up transistor element comprising a Darlington transistor pair for sourcing current to the output of the circuit from a high potential source V.sub.cc, typically 5 volts +0.5 volts for providing high level voltage signals. A pull-down transistor element sinks current from the circuit output to low potential typically ground or 0 volts for establishing low level voltage signals at the output. The phase splitter transistor element controls the respective states of the pull-up and pull-down transistor elements in response to data signals at the TTL circuit input.
On the other hand, the typical ECL gate or circuit includes a pair of transistors with common emitter coupling providing alternative transistor collector paths from a high level voltage or high potential at ground or 0 volts. The transistors are operatively coupled for switching current between the collector paths according to input signals at the base of one of the transistors. An ECL current source is coupled between the common emitter coupling and a negative voltage such as -5 volts +0.5 volts for generating current in the alternate transistor collector paths.
One of the ECL gate transistors is selected to be the input signal transistor for receiving ECL input data signals at the base of the input signal transistor. The other transistor constitutes a reference transistor and the negative reference voltage signal typically in the range of -1.2 to -2 volts applied to the base of the reference transistor establishes the relative location of high and low level signals in the negative voltage range. The output of the ECL gate or circuit is obtained from the collector nodes of the ECL transistor pair typically through emitter follower buffer transistors which provide current gain and shift the voltage levels. A feature and advantage of the ECL gate or circuit is that complementary output signals are available from the collector nodes. Furthermore, the input signal transistor may comprise multiple parallel transistors for multiple inputs or transistors arranged to provide desired logic functions and combinations. Further description of ECL gates and circuits can be found, for example, in the F100K ECL USER'S HANDBOOK, Copyright 1982, Fairchild Camera and Instrument Corporation, Advanced Bi-polar Division, 441 Whisman Road, Mountain View, California 94042, Chapter 2, "Circuit Basics", and the F100K ECL DATA BOOK, Chapter 1, 37 Family Overview", by the same publisher.
To obtain the advantages of both TTL and ECL circuits, gates, internal buffers and output devices, translators are required for translating the logic data signals from the voltage levels of one logic circuit family to voltage levels compatible with the other. Such a TTL to ECL translator according to the prior art is illustrated in FIG. 1. Generally, the conventional TTL to ECL translator 10 comprises an ECL input gate G1, operating however at positive TTL voltage levels, for receiving TTL voltage level logic input signals TTL V.sub.in at the input 12 compatible with TTL circuits. An ECL output gate G2 operating in the ECL negative voltage range delivers corresponding ECL voltage level logic output signals ECL V.sub.out at the complementary outputs 14 and 14c compatible with ECL circuits.
The ECL input gate G1 operating in the positive TTL voltage range includes a pair of transistors Q1 and Q2, with common emitter coupling 15, providing alternate transistor collector paths 16 and 18. ECL current source I1 generates the switching source current through either of the alternate collector paths 16 and 18 according to the conducting state of transistors Q1 and Q2. The conducting state of transistors Q1 and Q2 is controlled by input signals TTL V.sub.in in the positive TTL voltage range applied to the base of transistor Q1 at input 12.
ECL input gate G1 operates in the positive TTL voltage range between the high level voltage source V.sub.cc which may be for example +5 volts +0.5 volts and ground potential at node 20. The ECL current source I1 is connected between the common emitter node 15 and ground or low level potential node 20 and along with collector resistor RL determines the differential range or swing between high and low level logic signals in the TTL positive voltage range at the output of ECL input gate G1 which are applied to the base of emitter follower buffer transistor Q5. The positive reference voltage threshold and relative location of high and low level signals in the positive TTL voltage range is set by the base collector shorted (BCS) transistors Q3 and Q4 and reference resistor R.sub.ref coupled to the base of reference transistor Q2.
To provide translation down of the TTL voltage level logic input signals to ECL voltage levels a translating current source I2 and translating resistor R1 are provided at the output from ECL gate G1 and emitter follower buffer transistor Q5. The output signals from ECL input gate G1 and buffer transistor Q5 are translated down to the desired ECL negative voltage range by the selected value of the translating resistor R1 and the magnitude of current I2. Generally, an ECL output gate or stage G2 is provided to restore the edge rate of the translated ECL negative voltage level logic signals and provide higher power drive capability.
The ECL output gate G2 operates in the negative ECL voltage range between high level ground potential coupled at node 21 and low level voltage source V.sub.ee selected, for example, typically at -5 volts +0.5 volts. ECL output gate G2 is formed by the transistor pair Q6 and Q7 providing alternate collector paths through collector resistors RL1 and RL2 respectively. The ECL output gate current source I3 is coupled between the common emitter nodes 17 of ECL output gate G2 and low level voltage source V.sub.ee to provide the source current for switching between the alternate collector paths.
Transistor Q6 is the input transistor of ECL gate G2 and the translated signals are applied to the base of transistor Q6 for switching the source current I3 between the alternate transistor collector paths providing complementary ECL voltage level logic output signals at the complementary outputs 14 and 14c. With a high level or logic 1 TTL input signal TTL V.sub.in in the positive voltage range applied to the input 12 of ECL input gate G1, a high level or logic 1 ECL output signal ECL V.sub.out in the ECL negative voltage range appears at the "True" output 14 of ECL output gate G2 while a low level or logic 0 ECL signal in the ECL negative voltage range appears at the "False" output 14c of ECL output gate G2. Conversely, a low level or logic 0 input signal in the positive TTL voltage range at input 12 of ECL input gate G1 produces a low level or logic 0 ECL output signal in the negative ECL voltage range at the "True" output 14 of ECL output gate G2 while a high level or logic 1 ECL output signal appears at the "False" output 14c.
To reduce power consumption the translating current source and translating current I2 must be small in value while the translating resistor R1 is large. The time constant at the junction of R1 and I2 which is determined by the value of R1 and the capacitance at this junction is therefore also large. A relatively long rise and fall time between high and low level logic signals therefore results at this junction. Furthermore, the logic signal voltage swing in the TTL voltage range at ECL input gate G1 must be made large so that upon translation down to the ECL negative voltage range, there is sufficient range between the ECL high and low level voltage signals on either side of the reference voltage V.sub.ref so that the ECL output gate G2 can operate for all possible variations of the voltage source V.sub.cc. The combination of large time constant in the translation current path and large logic signal voltage swing in the ECL gates results in an undesirably long propagation delay across the conventional TTL to ECL translator.